Gate Driver On Array (GOA) technology is a kind of technology that the thin film transistor liquid crystal display array (Array) process is utilized to manufacture the Gate row scan drive signal circuit on the array substrate to realize the drive manner to scan the gates row by row.
Please refer to FIG. 1, which is a circuit diagram of a GOA circuit according to prior art. The GOA circuit of prior art comprises a plurality of GOA circuit units which are cascade coupled, wherein the nth level GOA circuit unit outputting a nth level horizontal scan signal comprises: a first thin film transistor T1, of which a gate is coupled to a signal output point Gn−2 of the n−2th level GOA circuit unit, and a source and a drain are respectively coupled to a node Hn and inputted with a forward scan control signal U2D; a second thin film transistor T2, of which a gate is coupled to the node Qn, and a source and a drain are respectively coupled to a signal output point Gn of the nth level GOA circuit unit and inputted with a clock signal CKV2; a third thin film transistor T3, of which a gate is coupled to a signal output point Gn+2 of the n+2th level GOA circuit unit, and a source and a drain are respectively coupled to the node Hn and inputted with the forward scan control signal D2U; a fourth thin film transistor T4, of which a gate is coupled to a node Pn, and a source and a drain are respectively coupled to the signal output point Gn and the constant low voltage level VGL; a fifth thin film transistor T5, of which a gate is coupled to a constant high voltage level VGH, and a source and a drain are respectively coupled to the node Hn and a node Qn; a sixth thin film transistor T6, of which a gate is coupled to the node Pn, and a source and a drain are respectively coupled to the node Hn and the constant low voltage level VGL; a seventh thin film transistor T7, of which a gate is coupled to the node Hn, and a source and a drain are respectively coupled to the node Pn and a constant low voltage level VGL; an eighth thin film transistor T8, of which a gate is inputted with a clock signal CKV4, and a source and a drain are respectively coupled to the node Pn and the constant high voltage level VGH; a first capacitor C1, of which two ends are respectively coupled to the node Qn and the signal output point Gn; a second capacitor C2, of which two ends are respectively coupled to the node Pn and the constant low voltage level VGL. The node Qn is the point employed to control the output of the gate drive signal; the node Pn is the point employed to maintain the stability of the low voltage levels of the point Qn and the point Gn. FIG. 1 depicts the structure of the GOA circuit unit with the nth level GOA circuit unit corresponding to the output of the level Gn to be an illustration. The structure of the adjacent n+1th level GOA circuit unit corresponding to the output of the level Gn+1 is the same as what is shown in FIG. 1 but only the different clock signal is utilized at work. The description for the structure of the n+1th level GOA circuit unit is omitted here.
Please refer to FIG. 2, which is a forward scan sequence diagram of the GOA circuit in FIG. 1. With combination of FIG. 1, the specific work process (forward scan) of the circuit is introduced below:
the output of the level Gn is illustrated; as forward scan, U2D is the high voltage level, and D2U is the low voltage level;
stage 1, pre-charge stage, Gn−2 and U2D are the high voltage levels at the same time, and T1 is on, and the point Hn is pre-charged. As the point Hn is the high voltage level, T5 is in an on state, and the point Qn is pre-charged. As the point Hn is the high voltage level, T7 is in an on state, and the point Pn is pulled down;
stage 2, Gn outputs the high voltage level: in stage 1, the point Qn is pre-charged, and C1 has a certain maintaining function to the electrical charges, and T2 is in an on state, and the high voltage level of CKV2 is outputted to the end Gn;
stage 3, Gn outputs the low voltage level: C1 has the maintaining function to the high voltage level to the point Qn, and the low voltage level of CKV2 pulls down the point Gn;
stage 4, the point Qn is pulled down to VGL: as Gn+2 is the high voltage level, D2U is the low voltage level, and T3 is in an on state, and thus, the point Qn is pulled down to be VGL;
stage 5, the point Qn and the point of Gn maintain the low voltage level: after the point Qn becomes the low voltage level, T7 is in an off state, and as CKV4 jumps to the high voltage level, T8 is on, and the point Pn is charge, and then both T4 and T6 are in an on state, which can ensure the low voltage level stabilities of the point Qn and the point Gn, and meanwhile, C2 has a certain maintaining function to the high voltage level of the point Pn.
For the n+1th level GOA circuit unit corresponding to the output of the level Gn+1, the used clock signals are CKV1 and CKV3, and the work process can be obtained with combination of FIG. 2.
Please refer to FIG. 3, which is a backward scan sequence diagram of the GOA circuit in FIG. 1. With combination of FIG. 1, the specific work process (backward scan) of the circuit is introduced below:
the output of the level Gn is illustrated; as forward scan, D2U is the high voltage level, and U2D is the low voltage level;
stage 1, pre-charge stage, Gn+2 and D2U are the high voltage levels at the same time, and T3 is on, and the point Hn is pre-charged. As the point Hn is the high voltage level, T5 is in an on state, and the point Qn is pre-charged. As the point Hn is the high voltage level, T7 is in an on state, and the point Pn is pulled down;
stage 2, Gn outputs the high voltage level: in stage 1, the point Qn is pre-charged, and C1 has a certain maintaining function to the electrical charges, and T2 is in an on state, and the high voltage level of CKV2 is outputted to the end Gn;
stage 3, Gn outputs the low voltage level: C1 has the maintaining function to the high voltage level to the point Qn, and the low voltage level of CKV2 pulls down the point Gn;
stage 4, the point Qn is pulled down to VGL: as Gn−2 is the high voltage level, U2D is the low voltage level, and T1 is in an on state, and thus, the point Qn is pulled down to be VGL;
stage 5, the point Qn and the point of Gn maintain the low voltage level: after the point Qn becomes the low voltage level, T7 is in an off state, and as CKV4 jumps to the high voltage level, T8 is on, and the point Pn is charge, and then both T4 and T6 are in an on state, which can ensure the low voltage level stabilities of the point Qn and the point Gn, and meanwhile, C2 has a certain maintaining function to the high voltage level of the point Pn.
For the n+1th level GOA circuit unit corresponding to the output of the level Gn+1, the used clock signals are CKV1 and CKV3, and the work process can be obtained with combination of FIG. 3.
The high, the low voltage levels outputted by Gn of the GOA circuit according prior art respectively are VGH and VGL, and are two stage drive. The feed through voltage corresponded with such gate drive manner is larger, and leads to the inconsistency of the optimized common voltages (Vcom) corresponding to various regions of the panel, which means that the two stage drive can easily cause the worse uniformity of Vcom of the panel and influence the display quality.